25
9152BINDCO02/10
ATA8743
12.4.1
SREG AVR Status Register
" Bit 7 I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
" Bit 6 T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
" Bit 5 H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the Instruction Set Description for detailed information.
" Bit 4 S: Sign Bit, S = N ?/SPAN> V
The S-bit is always an exclusive or between the Negative Flag N and the Twos Complement
Overflow Flag V. See the Instruction Set Description for detailed information.
" Bit 3 V: Twos Complement Overflow Flag
The Twos Complement Overflow Flag V supports twos complement arithmetics. See the
Instruction Set Description for detailed information.
" Bit 2 N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
Instruction Set Description for detailed information.
" Bit 1 Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction
Set Description for detailed information.
" Bit 0 C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit
7
6
5
4
3
2
1
0
0x3F (0x5F)
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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